This is because we are fundamentally describing hardware circuits when we use verilog. Unlike in other programming languages, we also need to define the number of bits we have in our data representation. We can express this data as either a binary, hexadecimal or octal value. When we write verilog, we often need to represent digital data values in our code.
As a result, there is often no need necessary to explicitly perform type conversions in verilog. When we assign data to a signal in verilog, the data is implicitly converted to the correct type in most cases. We can also use types which interpret our data as if it were a numeric value. We can use types which interpret data purely as logical values, for example. The type which we specify is used to define the characteristics of our data. This includes a discussion of data respresentation, net types, variables types, vectors types and arrays.Īlthough verilog is considered to be a loosely typed language, we must still declare a data type for every port or signal in our verilog design. In this post, we talk about the most commonly used data types in Verilog.
